MITSUBISHI
〈DIGITAL
ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
TEST CIRCUIT
Vcc
Qn
R
L
=1kΩ
C
L
= 30pF : t
AC
, t
OH
SW1
Qn
SW2
C
L=
5
p
F
:
t
OEN,
t
ODIS
R
L
=1kΩ
Input pulse level:
0 ~ 3V
Input pulse rise time and fall time: 3ns
Measurement reference level, input: 1.3V
Measurement reference level, output: 1.3V (Note: t
ODIS
(LZ) is tested at 10% output
amplitude, and t
ODIS
(HZ) is tested at 90%
output amplitude.)
Load capacitance C
L
includes floating capacitance and probe input capacitance.
Parameter
t
ODIS(LZ)
t
ODIS(HZ)
t
OEN(ZL)
t
OEN(ZH)
SW1
Closed
Open
Closed
Open
SW2
Open
Closed
Open
Closed
TEST CONDITIONS FOR OUTPUT DISABLE TIME t
ODIS
AND OUTPUT ENABLE TIME t
OEN
3V
RCK
1.3V
1.3V
GND
3V
RE
GND
t
ODIS(HZ)
90%
1.3V
t
OEN(ZH)
V
OH
Qn
t
ODIS(LZ)
t
OEN(ZL)
Qn
10%
1.3V
V
OL
4
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
