Read Cycle 1
(Address Controlled, /CS=/OE=V
IL
, /WE=V
IH
)
t
RC
Address
t
OH
Data Out
Previous Data Valid
t
AA
Data Valid
Timing Waveforms
Read Cycle 2
(/WE = V
IH
)
t
RC
Address
t
AA
t
ACS
/CS
t
OHZ
t
OE
/OE
t
OLZ
t
CLZ(4,5)
Data Out
Valid Data
t
OH
t
CHZ(3,4,5)
NOTES(READ
CYCLE)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
CHZ
(Max.) is less than t
CLZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±200mV
from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CS=V
IL
.
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. /CS=/CS1~4
PAGE 6
Issue 5.2 April 2001
MOSAIC [ MOSAIC ]
