Write Cycle 3
(/CS = Controlled)
t
WC
Address
t
AW
t
CW(3)
/CS
t
AS(4)
/WE
t
DW
High Z
Data In
t
LZ
High Z
Data Out
t
WHZ(6)
High Z(8)
Valid Data
t
DH
High Z
t
WP(2)
t
WR(5)
NOTES(WRITE
CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. t
WP
is measured from the beginning of write to the end of
write.
3. t
CW
is measured from the later of /CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as /CS or /WE going high.
6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11./CS=/CS1~4
Note: /CS = /CS1~4
PAGE 9
Issue 5.2 April 2001
MOSAIC [ MOSAIC ]
