Preliminary
MOSEL VITELIC INC.
MSU3022/U3032/U3042
Block Diagram
COM1,2,3
LCD
LCD
patt'n
Reg'rs
15 x 8
LCD
Timer
6 bits
Decoder &
Register
RAM
Register
Decoder
Timing
64 x 4
ROM
SEG1-25
Gen.
1K x 15
ø3
Register
ESR 1x8
to pertinent blocks
Reset
Circuit
RES
HIB 1x8
PHB 1x8
PC
Increamenter
Vdd1,2
Vss1,2,3,V
CUP1,2
BAK
Power
Circuit
Acc
1x4
to whole chip
Program
Counter
10 bits
Buffer1
Buffer2
to pertinent blocks
Stack
4 x 10
VBZ/INT
Interrupt
Circuit
ALU
S.P.
ROSC
CAP
X1
ø3
2 bits
Timming
to whole chip
Generator
Carry
X2
Word &
Sentence
Decoder
VBZ/INT
Voice
ROM
B0000hx5
Port M
Port S
Port P
Latch
Port B
Port A
Latch
Light
Latch
Latch
Latch
Latch
Output
Buffer
Port M
Buffer
Port S
Buffer
Port P
Driver
Port B
Driver
Port A
Driver
Light
Driver
4
4
4
4
4
LGT
V1V2 Cout
Specifications subject to change without notice, contact your sales representatives for the most recent information.
3/16
PID 262(*) 08/97
MOSEL [ MOSEL VITELIC, CORP ]
