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V29C51002T-90J 参数 Datasheet PDF下载

V29C51002T-90J图片预览
型号: V29C51002T-90J
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位262,144 ×8位的5伏CMOS FLASH MEMORY [2 MEGABIT 262,144 x 8 BIT 5 VOLT CMOS FLASH MEMORY]
分类和应用: 内存集成电路
文件页数/大小: 16 页 / 76 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MOSEL VITELIC
Functional Description
The V29C51002T/V29C51002B consists of 512
equally-sized sectors of 512 bytes each. The 16 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.
The V29C51002 is available in two versions: the
V29C51002T with the Boot Block address starting
from 3C000H to 3FFFFH, and the V29C51002B
with the Boot Block address starting from 00000H
to 3FFFFH.
V29C51002T
16KB Boot Block
512 Byte
512 Byte
V29C51002T/V29C51002B
V29C51002B
3FFFFH
3C000H
512 Byte
512 Byte
03FFFH
512 Byte
00000H
00000H
512 Byte
16KB Boot Block
51002-15
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
16KB Boot Block = 32 Sectors
Byte Write Cycle
The V29C51002T/V29C51002B is programmed
on a byte-by-byte basis. The byte write operation is
initiated by using a specific four-bus-cycle
sequence: two unlock program cycles, a program
setup command and program data program cycles
(see Table 2).
During the byte write cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.
Command Sequence
The V29C51002T/V29C51002B does not
provide the “reset” feature to return the chip to its
normal state when an incomplete command
sequence or an interruption has happened. In this
case, normal operation (Read Mode) can be
restored by issuing a “non-existent” command
sequence, for example Address: 5555H, Data FFH.
Sector Erase Cycle
The V29C51002T/V29C51002B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
Table 1. Operation Modes Decoding
Decoding Mode
Read
Byte Write
Standby
Autoselect Device ID
Autoselect Manufacture ID
Enabling Boot Block Protection Lock
Disabling Boot Block Protection Lock
Output Disable
CE
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
H
V
IL
OE
V
IL
V
IH
X
V
IL
V
IL
V
H
V
H
V
IH
WE
V
IH
V
IL
X
V
IH
V
IH
V
IL
V
IL
V
IH
A
0
A
0
A
0
X
V
IH
V
IL
X
X
X
A
1
A
1
A
1
X
V
IL
V
IL
X
X
X
A
9
A
9
A
9
X
V
H
V
H
V
H
V
H
X
I/O
READ
PD
HIGH-Z
CODE
CODE
X
X
HIGH-Z
NOTES:
1. X = Don’t Care, V
IH
= HIGH, V
IL
= LOW, V
H
= 12.5V Max.
2. PD: The data at the byte address to be programmed.
V29C51002T/V29C51002B Rev. 2.1 October 2000
9