MOSEL VITELIC
SPD-Table for PC133 modules: (Continued)
V43644R04VCTG-75
Hex Value
Byte Number
31
32
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Function Described
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
Reserved
Intel Specification for Frequency
Reserved
Unused Storage Location
SPD Entry Value
32 MByte
1.5 ns
0.8 ns
1.5 ns
0.8 ns
4Mx64
08
15
08
15
08
00
Revision 2
02
8B
Mosel Vitelic
40
00
V43644R04VCTG-75
00
64
00
00
T
A
= 0
°
C to 70
°
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
Limit Values
Symbol
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
DC Characteristics
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (I
OUT
= –2.0 mA)
Output Low Voltage (I
OUT
= 2.0 mA)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
Min.
2.0
–0.5
2.4
—
–40
Max.
V
CC
+0.3
0.8
—
0.4
40
Unit
V
V
V
V
µ
A
µ
A
–40
40
V43644R04VCTG-75 Rev. 1.1 September 2000
5
MOSEL [ MOSEL VITELIC, CORP ]
