MOSEL VITELIC
Notes:
V43644R04VCTG-75
1. The specified values are valid when addresses are changed no more than once during t
CK
(min.) and when No
Operation commands are registered on every rising clock edge during t
RC
(min). Values are shown per module bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t
RC
(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100
µs
is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V
IL
= 0.4V and V
IH
= 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between V
IH
and V
IL
. All AC measurements assume t
T
= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
tCH
2.4V
CLOCK
0.4V
+ 1.4 V
50 Ohm
Z=50 Ohm
I/O
50 pF
tCL
tSETUP
tHOLD
t
T
INPUT
1.4V
tAC
tLZ
tOH
tAC
I/O
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (t
T
/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If t
T
is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self
Refresh Exit is not complete until a time period equal to t
RC
is satisfied once the Self Refresh Exit command is reg-
istered.
10.
11.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
t
DAL
is equivalent to t
DPL
+ t
RP
.
V43644R04VCTG-75 Rev. 1.1 September 2000
9
MOSEL [ MOSEL VITELIC, CORP ]
