MOSEL VITELIC
Functional Description
The V53C8126H is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C8126H reads and writes
data by multiplexing an 17-bit address into a 9-bit
row and an 8-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the
CAS
edge occurs, the delay time from
RAS
to
CAS
has little effect on the access time.
V53C8126H
Write Cycle
A Write Cycle is performed by taking
WE
and
CAS
low during a
RAS
operation. The column
address is latched by
CAS.
The Write Cycle can be
WE
controlled or
CAS
controlled depending on
whether
WE
or
CAS
falls later. Consequently, the
input data must be valid at or before the falling edge
of
WE
or
CAS,
whichever occurs last. In the
CAS-
controlled Write Cycle, when the leading edge of
WE
occurs prior to the
CAS
low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with
RAS
or
CAS
will maintain the output in the High-Z state.
In the
WE
controlled Write Cycle,
OE
must be in
the high state and t
OED
must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing
RAS
low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum t
RAS
time has
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t
RP
/t
CP
has elapsed.
Refresh Cycle
To retain data, 512 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A
0
through A
8
) with
RAS
at least once every 8 ms.
Any Read, Write, Read-Modify-Write or
RAS-
only cycle refreshes the addressed row.
2. Using a
CAS-before-RAS
Refresh Cycle. If
CAS
makes a transition from low to high to low after
the previous cycle and before
RAS
falls,
CAS-
before-RAS refresh is activated. The
V53C8126H uses the output of an internal 9-bit
counter as the source of row addresses and
ignore external address inputs.
CAS-before-RAS
is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the
cycle. A
CAS-before-RAS
counter test mode is
provided to ensure reliable operation of the internal
refresh counter.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a
RAS/CAS
operation. The column address must be held for a
minimum specified by t
AR
. Data Out becomes valid
only when t
OAC
, t
RAC
, t
CAA
and t
CAC
are all satisifed.
As a result, the access time is dependent on the
timing relationships between these parameters. For
example, the access time is limited by t
CAA
when
t
RAC
, t
CAC
and t
OAC
are all satisfied.
V53C8126H Rev. 1.1 July 1997
15
MOSEL [ MOSEL VITELIC, CORP ]
