V53C8126H
MOSEL VITELIC
OE signal has no effect on any data stored in the
output latches. A WE low level can also disable the
output drivers when CAS is low. During a Write
cycle, if WE goes low at a time in relationship to
CAS that would normally cause the outputs to be
active, it is necessary to use OE to disable the
output drivers prior to the WE low transition to allow
Data In Setup Time (tDS) to be satisfied.
Fast Page Mode Operation
Fast Page Mode operation permits all 256
columns within a selected row of the device to be
randomly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates
the need to reapply it for each cycle. The column
address buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode
operation, Read, Write, Read-Modify-Write or
Read-Write-Read cycles are possible at random
addresses within a row. Following the initial entry
cycle into Fast Page Mode, access is tCAA or tCAP
controlled. If the column address is valid prior to the
rising edge of CAS, the access time is referenced to
the CAS rising edge and is specified by tCAP. If the
column address is valid after the rising CAS edge,
access is timed from the occurrence of a valid
address and is specified by tCAA. In both cases, the
falling edge of CAS latches the address and
enables the output.
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C8126H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and IDD will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
Table 1. V53C8126H Data Output
Fast Page Mode provides sustained data rates
up to 40 MHz for applications that require high data
rates such as bit-mapped graphics or high-speed
signal processing. The following equation can be
used to calculate the maximum data rate:
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
256
Data Rate =
CAS-Controlled Write
Cycle (Early Write)
High-Z
tRC + 255 x tPC
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Data Output Operation
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
The V53C8126H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition
enables the transfer of data to and from the
selected row address in the Memory Array. A RAS
high transition disables data transfer and latches
the output data if the output is enabled. After a
memory cycle is initiated with a RAS low transition,
a CAS low transition or CAS low level enables the
internal I/O path. A CAS high transition or a CAS
high level disables the I/O path and the output driver
if it is enabled. A CAS low transition while RAS is
high has no effect on the I/O data path or on the
output drivers. The output drivers, when otherwise
enabled, can be disabled by holding OE high. The
Fast Page Mode
Read
Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write)
High-Z
Fast Page Mode Read-
Modify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C8126H Rev. 1.1 July 1997
16
MOSEL [ MOSEL VITELIC, CORP ]
