MC34023 MC33023
OPERATING DESCRIPTION
The MC33023 and MC34023 series are high speed, fixed
limiting the duty cycle. The time it takes for a capacitor to
reach full charge is given by:
frequency, single–ended pulse width modulator controllers
optimized for high frequency operation. They are specifically
designed for Off–Line and DC–to–DC converter applications
offering the designer a cost effective solution with minimal
external components. A representative block diagram is
shown in Figure 18.
5
t
(4.5 • 10 ) C
Soft-Start
A Soft–Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft–Start circuit to latch so that the Soft–Start capacitor
stays discharged. The first condition is activation of an
Oscillator
undervoltage lockout of either V
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
or V . The second
CC
ref
The oscillator frequency is programmed by the values
selected for the timing components R and C . The R pin is
T
T
T
set to a temperature compensated 3.0 V. By selecting the
value of R , the charge current is set through a current mirror
thesesignalsisremovedand,thevoltageatC
than 0.5 V.
isless
Soft–Start
T
for the timing capacitor C . This charge current runs
T
continuously through C . The discharge current is ratioed to
T
PWM Comparator and Latch
be 10 times the charge current, which yields the maximum
A PWM circuit typically compares an error voltage with a
ramp signal. The outcome of this comparison determines the
state of the output. In voltage mode operation the ramp signal
is the voltage ramp of the timing capacitor. In current mode
operation the ramp signal is the voltage ramp induced in a
current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the error amplifier output voltage
minus 1.25 V, the PWM comparator will cause the PWM latch
to set, disabling the outputs. Once the PWM latch is set, only
a blanking pulse by the oscillator can reset it, thus initiating
the next cycle.
duty cycle of 90%. C is charged to 2.8 V and discharged to
1.0 V. During the discharge of C , the oscillator generates an
T
internal blanking pulse that resets the PWM Latch and,
inhibits the outputs. The threshold voltage on the oscillator
comparator is trimmed to guarantee an oscillator accuracy of
5.0% at 25°C.
T
Additional dead time can be added by externally
increasing the charge current to C as shown in Figure 23.
T
This changes the charge to discharge ratio of C which is set
T
internally to I
ratio will be:
/10 I
charge
. The new charge to discharge
charge
I
I
l
additiona
charge
)
% Deadtime
10 (I
charge
Current Limiting and Shutdown
A bidirectional clock pin is provided for synchronization or
for master/slave operation. As a master, the clock pin
A pin is provided to perform current limiting and shutdown
operations. Two comparators are connected to the input of
this pin. The reference voltage for the current limit
comparator is not set internally. A pin is provided so the user
can set the voltage. When the voltage at the current limit
input pin exceeds the externally set voltage, the PWM latch is
set, disabling the output. In this way cycle–by–cycle current
limiting is accomplished. If a current limit resistor is used in
series with the power devices, the value of the resistor is
found by:
provides a positive output pulse during the discharge of C .
T
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge C .
T
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 27, 28 and 29 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It features
a typical DC voltage gain of 95 dB and a gain bandwidth
product of 8.3 MHz with 75 degrees of phase margin
(Figure 3). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
I
Limit Reference Voltage
R
Sense
I
pk (switch)
If the voltage at this pin exceeds 1.4 V, the second
comparator is activated. This comparator sets a latch which,
in turn, causes the soft start capacitor to be discharged. In
this way a “hiccup” mode of recovery is possible in the case
of output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
have a common mode voltage (V
5.5 V. The Error Amplifier Output is provided for external loop
compensation.
) input range of 1.5 V to
CM
Soft–Start Latch
Soft–Start is accomplished in conjunction with an external
capacitor. The Soft–Start capacitor is charged by an internal
9.0 µA current source. This capacitor clamps the output of
the error amplifier to less than its normal output voltage, thus
1.4 V
I
shutdown
R
Sense
8
MOTOROLA ANALOG IC DEVICE DATA
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