Table D-16 Effect of DDRQS on QSM Pin Function
QSM Pin
MISO
Mode
Master
Slave
MOSI
Master
Slave
SCK
1
Master
Slave
PCS0/SS
Master
Slave
PCS[3:1]
Master
Slave
TXD
2
RXD
Transmit
Receive
DDQS7
None
DDQS
[4:6]
DDQS3
DDQS2
DDQS1
DDRQS
Bit
DDQS0
Bit
State
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
NA
Pin Function
Serial Data Input to QSPI
Disables Data Input
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
QSPI Slave Select Input
Disables Select Input
Disables Chip-Select Output
Chip-Select Output
Inactive
Inactive
Serial Data Output from SCI
Serial Data Input to SCI
D
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI
serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 =1), in which case it
becomes SCI serial output TXD.
DDRQS determines the direction of the TXD pin only when the SCI transmitter is dis-
abled. When the SCI transmitter is enabled, the TXD pin is an output.
D.4.10 SPCR0
— QSPI Control Register 0
15
MSTR
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
14
WOMQ
13
BITS
10
9
CPOL
8
CPHA
7
SP
$YFFC18
0
SPCR0 contains parameters for configuring the QSPI and enabling various modes of
operation. The CPU has read/write access to SPCR0, but the QSM has read access
only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to
SPCR0 while the QSPI is enabled disrupts operation.
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device.
1 = QSPI is system master.
MOTOROLA
D-32
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA, INC ]
