Both writes must occur before time-out in the order listed, but any number of instruc-
tions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and soft-
ware watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
Table 4-3 MODCLK Pin and SWP Bit During Reset
MODCLK
SWP
1 (÷ 512)
0 (÷ 1)
0 (External Clock)
1 (Internal Clock)
The SWT field selects the divide ratio used to establish software watchdog time-out
period. Time-out period is given by the following equations.
1
Time-out Period = ------------------------------------------------------------------------------------
EXTAL Frequency ⁄ Divide Ratio
4
or
Divide Ratio
Time-out Period = ------------------------------------------------
EXTAL Frequency
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new time-
out period can take effect.
Table 4-4 Software Watchdog Ratio
SWP
SWT
00
Ratio
9
2
0
0
0
0
1
1
1
1
11
2
01
13
2
10
15
2
11
18
2
00
20
2
01
22
2
10
24
2
11
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
MOTOROLA
4-6
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
