PITR
SWP
PTP
FREEZE
CLOCK
PRECLK MUX
÷
4
PITCLK
8-BIT MODULUS
COUNTER
PIT
INTERRUPT
EXTAL
CLOCK
DISABLE
PRESCALER (2
9
)
RESET
SWCLK
LPSTOP
SWT1
SWT0
SWE
15 STAGE
DIVIDER CHAIN (2
15
)
2
9
2
11
2
13
2
15
PIT BLOCK
Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer
4.2.11 Periodic Interrupt Timer
The periodic interrupt timer allows the generation of interrupts of specific priority at pre-
determined intervals. This capability is often used to schedule control system tasks
that must be performed within time constraints. The timer consists of a prescaler, a
modulus counter, and registers that determine interrupt timing, priority and vector as-
signment. Refer to
for further information
about interrupt exception processing.
The periodic interrupt modulus counter is clocked by a signal derived from the buffered
crystal oscillator (EXTAL) input pin unless an external frequency source is used. The
value of the periodic timer prescaler (PTP) bit in the periodic interrupt timer register
(PITR) determines system clock prescaling for the watchdog timer. One of two op-
tions, either no prescaling, or prescaling by a factor of 512, can be selected. The value
of PTP is affected by the state of the MODCLK pin during reset, as shown in
System software can change PTP value.
Table 4-5 MODCLK Pin and PTP Bit at Reset
MODCLK
0 (External Clock)
1 (Internal Clock)
PTP
1 (÷ 512)
0 (÷ 1)
4
Either clock signal (EXTAL or EXTAL
÷
512) is divided by four before driving the mod-
ulus counter (PITCLK). The modulus counter is initialized by writing a value to the pe-
riodic timer modulus timer modulus (PITM) field in the PITR. A zero value turns off the
periodic timer. When the modulus counter value reaches zero, an interrupt is generat-
ed. The modulus counter is then reloaded with the value in PITM and counting repeats.
If a new value is written to PITR, it is loaded into the modulus counter when the current
count is completed.
MC68331
USER’S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA
4-7
MOTOROLA [ MOTOROLA, INC ]
