AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
10MHz
16MHz
20MHz
NUM
CHARACTERISTIC
UNIT
MIN
MAX
—
MIN
MAX
—
MIN
MAX
—
29
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
0
—
0
0
—
0
0
—
0
ns
ns
ns
ns
29A AS, LDS, UDS Negated to Data-In High Impedance (Read)
150
—
90
75
30
AS, LDS, UDS Negated to BERR Negated
—
—
2,5
DTACK Asserted to Data-In Valid (Setup Time on Read)
—
65
—
50
—
42
31
32
33
34
35
HALT and RESET Input Transition Time
Clock High to BG Asserted
0
150
35
0
150
30
0
150
25
ns
ns
—
—
—
Clock High to BG Negated
—
35
—
30
—
25
ns
BR Asserted to BG Asserted
BR Negated to BG Negated
1.5
1.5
3.5
3.5
1.5
1.5
3.5
3.5
1.5
1.5
3.5
3.5
Clks
Clks
7
36
38
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
—
55
—
50
—
42
ns
39
44
BG Width Negated
1.5
0
—
55
—
1.5
0
—
50
—
1.5
0
—
42
—
Clks
ns
AS, LDS, UDS Negated to AVEC Negated
Asynchronous Input Setup Time
5
5
5
5
ns
47
2,3
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
48
52
53
55
Data-In Hold from Clock High
0
0
—
—
—
—
0
0
—
—
—
—
0
0
—
—
—
—
ns
ns
Data-Out Hold from Clock High (Write)
R/W Asserted to Data Bus Impedance Change (Write)
HALT, RESET Pulse Width
20
10
10
10
0
ns
4
10
Clks
56
58
7
BR Negated to AS, LDS, UDS, R/W Driven
BR Negated to FC Driven
1.5
1
—
—
1.5
1
—
—
1.5
1
—
—
Clks
Clks
7
58A
Applies to 3.3V and 5V.
NOTES: 1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
3.
Actual value depends on clock period.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
5.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6.
7.
When AS and R/W are equally loaded (
±20%), subtract 5 ns from the values given in these columns.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
MOTOROLA [ MOTOROLA ]
