4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 on page 10-6 with Figure 7.
DRIVE
TO 2.4 V
2.0 V
CLK
0.8 V
DRIVE TO
0.5 V
OUTPUTS(1) CLK
A
B
2.0 V
0.8 V
VALID
OUTPUT
0.8 V
2.0 V
2.0 V
VALID
OUTPUT n 0.8 V
n+1
B
2.0 V
VALID
OUTPUT n
0.8 V
A
2.0 V
0.8 V
OUTPUTS(2) CLK
VALID
OUTPUT n+1
C
DRIVE TO
2.4 V
INPUTS(3) CLK
DRIVE TO
0.5 V
0.8 V
2.0 V
D
2.0 V
0.8 V
VALID
INPUT
C
2.0 V
INPUTS(4) CLK
0.8 V
D
2.0 V
0.8 V
DRIVE
TO 2.4 V
DRIVE
TO 0.5 V
VALID
INPUT
2.0 V
ALL SIGNALS(5)
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
Figure 7. Drive Levels and Test Points for AC Specifications - applies to all parts
9
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
MOTOROLA [ MOTOROLA, INC ]
