®
®
ADS-933
DYNAMIC PERFORMANCE
(Cont.)
ANALOG OUTPUT
Overvoltage Recovery Time
A/D Conversion Rate
Internal Reference
Voltage
Drift
External Current
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Output Coding
POWER REQUIREMENTS
Power Supply Ranges
}
+5V Supply
–5V Supply
Power Supply Currents
+5V Supply
–5V Supply
Power Dissipation
Power Supply Rejection
MIN.
+25°C
TYP.
MAX.
0 TO +70°C
MIN.
TYP.
MAX.
–55 TO +125°C
MIN.
TYP.
MAX.
UNITS
—
3
3.15
—
—
—
—
+3.2
±30
5
333
—
—
—
—
—
3
—
—
—
—
—
+3.2
±30
5
333
—
—
—
—
—
3
—
—
—
—
—
+3.2
±30
5
333
—
—
—
—
ns
MHz
Volts
ppm/°C
mA
+2.4
—
—
—
—
—
+2.4
—
—
+2.4
—
—
—
+0.4
—
—
+0.4
—
—
+0.4
—
–4
—
—
–4
—
—
–4
—
+4
—
—
+4
—
—
+4
Offset Binary / Complementary Offset Binary / Two's Complement / Complementary Two's Complement
Volts
Volts
mA
mA
+4.75
–4.75
—
–140
—
—
+5.0
–5.0
+220
–150
1.85
—
+5.25
–5.25
260
—
2.0
±0.07
+4.75
–4.75
—
–140
—
—
+5.0
–5.0
+220
–150
1.85
—
+5.25
–5.25
260
—
2.0
±0.07
+4.9
–4.9
—
–140
—
—
+5.0
–5.0
+220
–150
1.85
—
+5.25
–5.25
260
—
2.0
±0.07
Volts
Volts
mA
mA
Watts
%FSR/%V
Footnotes:
All power supplies must be on before applying a start convert pulse. All
supplies and the clock (START CONVERT) must be present during
warm-up periods. The device must be continuously converting during
this time.
When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA.
A 3MHz clock with a 50nsec positive pulse width is used for all
production testing. See Timing Diagram for more details.
Effective bits is equal to:
(SNR + Distortion) – 1.76 +
20 log
6.02
Full Scale Amplitude
Actual Input Amplitude
This is the time required before the A/D output data is valid once the
analog input is back within the specified range.
The minimum supply voltages of +4.9V and –4.9V for ±V
DD
are required for
–55°C operation only. The minimum limits are +4.75V and –4.75V when
operating at +125°C.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-933
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital ground
systems are connected to each other internally. For optimal
performance, tie all ground pins (2, 4, 7, 30 and 36) directly
to a large
analog
ground plane beneath the package.
Bypass all power supplies and the +3.2V reference output
to ground with 4.7µF tantalum capacitors in parallel with
0.1µF ceramic capacitors. Locate the bypass capacitors as
close to the unit as possible.
2. The ADS-933 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain calibration hardware,
make adjustments following warm-up. To avoid interaction,
always adjust offset before gain. Tie pins 5 and 6 to
ANALOG GROUND (pin 4) if not using offset and gain
adjust circuits.
3. Pin 35 (COMP. BITS) is used to select the digital output
coding format of the ADS-933. See Tables 2a and 2b.
When this pin has a TTL logic "0" applied, it complements
all of the ADS-933’s digital outputs.
When pin 35 has a logic "1" applied, the output coding is
complementary offset binary. Applying a logic "0" to pin
35 changes the coding to offset binary. Using the MSB
output (pin 29) instead of the MSB output (pin 28) changes
the respective output codings to complementary two's
complement and two's complement.
Pin 35 is TTL compatible and can be directly driven with
digital logic in applications requiring dynamic control over
its function. There is an internal pull-up resistor on pin 35
allowing it to be either connected to +5V or left open when
a logic "1" is required.
4. To enable the three-state outputs, connect OUTPUT
ENABLE (pin 34) to a logic "0" (low). To disable, connect
pin 34 to a logic "1" (high).
3
MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
