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ADS-933MM 参数 Datasheet PDF下载

ADS-933MM图片预览
型号: ADS-933MM
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 3MHz的采样A / D转换器 [16-Bit, 3MHz Sampling A/D Converters]
分类和应用: 转换器
文件页数/大小: 8 页 / 134 K
品牌: MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
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®
®
ADS-933
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized
and specified over operating temperature (case) ranges of 0
to +70°C and –55 to +125°C. All room-temperature (T
A
=
+25°C) production testing is performed without the use of heat
sinks or forced-air cooling. Thermal impedance figures for
each device are listed in their respective specification tables.
These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should
be used to ensure devices do not overheat. The ground and
power planes beneath the package, as well as all pcb signal
runs to and from the device, should be as heavy as possible
to help conduct heat away from the package. Electrically
insulating, thermally-conductive "pads" may be installed
underneath the package. Devices should be soldered to
boards rather than "socketed", and of course, minimal air flow
over the surface can greatly help reduce the package
temperature.
In more severe ambient conditions, the package/junction
temperature of a given device can be reduced dramatically
(typically 35%) by using one of DATEL's HS Series heat sinks.
See Ordering Information for the assigned part number. See
page 1-183 of the DATEL Data Acquisition Components
Catalog for more information on the HS Series. Request
DATEL Application Note AN-8, "Heat Sinks for DIP Data
Converters," or contact DATEL directly, for additional
information.
N
START
CONVERT
N+1
50ns typ.
N+2
N+3
N+4
N+5
Acquisition Time
170ns typ.
20ns typ.
INTERNAL S/H
Hold
161ns typ.
53ns typ.
EOC
Conversion Time
178ns typ.
265ns typ.
20ns typ.
OUTPUT
DATA
Data N-4 Valid
Data N-3 Valid
Data N-2 Valid
Data N-1 Valid
Data N Valid
68ns typ.
Notes: 1. Scale is approximately 50ns per division. fs = 3MHz.
Invalid
Data
2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data
from the first conversion to appear at the output of the A/D.
3. The start convert positive pulse width must be between either 20 and 60nsec or 200 and 310nsec
(when sampling at 3MHz) to ensure proper operation. For sampling rates lower than 3MHz, the start pulse
can be wider than 310nsec, however a minimum pulse width low of 20nsec should be maintained. A 3MHz
clock with a 50nsec positive pulse width is used for all production testing.
Figure 3. ADS-933 Timing Diagram
6