WidePort LANCAM
®
Family
GENERAL DESCRIPTION
The MU9C4485A/L, MU9C2485A/L, and MU9C1485A/L
WidePort LANCAMs are 64-bit wide content-addressable
memories (CAMs), featuring a 32-bit wide interface. This
interface doubles the available I/O bandwidth in many
applications while maintaining the same powerful enhanced
architecture and instruction set as the MU9C2480A/L.
Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In a RAM, the input to the device is an
address and the output is the data stored at that address. In a
CAM, the input is a data sample and the output is a flag to
indicate a match and the address of the matching data. As a
result, a CAM searches large databases for matching data in a
short, constant time period, no matter how many entries are in
the database. The ability to search data words up to 64 bits
wide allows large address spaces to be searched rapidly and
efficiently. A patented architecture links each CAM entry to
associated data and makes this data available for use after a
successful compare operation.
While the WidePort LANCAMs are optimized for LAN network
address filtering, they are also well suited for applications that
require high-speed data searching, such as virtual memories
and cache management, data compression and encryption,
database accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the WidePort LANCAM, the user loads the data into
the Comparand register, which is automatically compared to
all valid CAM locations. The device then indicates whether
or not one or more of the valid CAM locations contains data
that match the target data. The status of each CAM location
is determined by two validity bits at each memory location.
The two bits are encoded to render four validity conditions:
Valid, Skip, Empty, and Random Access, as shown in Table 1.
The memory can be partitioned into CAM and associated
RAM segments on 16-bit boundaries, but by using one of the
two available mask registers, the CAM/RAM partitioning can
be set at any arbitrary size between zero and 64 bits.
The WidePort LANCAM’s internal data path is 64 bits wide
for rapid internal comparison and data movement. A data
translation facility converts between IEEE 802.3 (CSMA/CD
“Ethernet”) and 802.5 (Token Ring) address formats. Vertical
cascading of additional WidePort LANCAMs in a daisy chain
fashion extends the CAM memory depth for large databases.
Cascading requires no external logic. Loading data to the
Control, Comparand, and mask registers automatically triggers
Skip Bit
0
0
1
1
Empty Bit
0
1
0
1
Entry Type
Valid
Empty
Skip
RAM
a compare. Compares may also be initiated by a command to
the device. Associated RAM data is available immediately
after a successful compare operation. The Status register reports
the results of compares including all flags and addresses. Two
mask registers are available and can be used in two different
ways: to mask comparisons or to mask data writes. The random
access validity type allows additional masks to be stored in
the CAM array where they may be retrieved rapidly.
A simple four-wire control interface and commands loaded
into the Instruction decoder control the device. A powerful
instruction set increases the control flexibility and minimizes
software overhead. Additionally, dedicated pins for match and
multiple-match flags enhance performance when the device is
controlled by a state machine. These and other features make
the WidePort LANCAM a powerful associative memory that
drastically reduces search delays.
G ND
D Q8
D Q7
D Q6
D Q5
D Q4
D Q3
D Q2
D Q1
D Q0
G ND
G ND
G ND
42
G ND
41
V CC
V CC
/C M
45
/ MA
44
/EC
/ FI
43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
G ND
G ND
D Q9
D Q 10
D Q 11
NC
V CC
V CC
TE S T2
NC
G ND
G ND
D Q 12
D Q 13
G ND
G ND
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
/ FF
/ MI
/ MF
/ MM
G ND
G ND
/R ESET
V CC
V CC
/E
/W
V CC
V CC
TE S T1
NC
D Q 31
D Q 30
G ND
G ND
80-Pin TQFP
8 0 -P IN TQ FP
(Top V ie w )
(Top View)
Table 1: Entry Types vs. Validity Bits
/W
LOW
LOW
HIGH
HIGH
/CM
Cycle Type
LOW
Command Write Cycle
HIGH
Data Write Cycle
LOW
Command Read Cycle
HIGH
Data Read Cycle
Table 2: I/O Cycles
D Q 14
D Q 15
D Q 16
NC
10
11
12
13
14
15
16
17
18
D Q 28
19
D Q 29
D Q 17
D Q 18
D Q 19
D Q 20
V CC
D Q 21
D Q 22
D Q 23
D Q 24
D Q 25
GN
D
D Q 26
D Q 27
GN
D
GN
D
GN
D
GN
D
Pinout Diagram
Rev. 2
2
GN
D
20
1
2
3
4
5
6
7
8
9
MUSIC [ MUSIC SEMICONDUCTORS ]
