MU9C RCP Family
Functional Description
FUNCTIONAL DESCRIPTION
Data is read from and written to the MU9C RCP through
the DQ31-0 lines. The Control bus, which is comprised of
Chip Enable (/E), two Chip Selects (/CS1, /CS2), Write
Enable (/W), Output Enable (/OE), Validity Bit Control
(/VB), Address Valid (/AV), Data Segment Control (DSC),
and the Address/Control inputs (AC bus) controls the
MU9C RCP. When the /AV line is LOW, the AC bus
carries an address for random access into the Memory
array; when it is HIGH, the AC bus conveys control
information. The MU9C RCP control states perform
Register Read/Write, Memory Read/Write, Data Move,
Comparison, Validity Bit Control, Initialization, and
Address Register Control. These functions are
summarized in Control State Overview on page 18.
Random access to memory locations occurs when the /AV
line is LOW; during a Write cycle, the validity of the
location is set by the /VB input. When the /AV line is
HIGH the control states allow read and write access to the
register set comprising Comparand register, seven mask
registers, a Configuration register, a Status register, an
Address register, a Device Select register, and an
Instruction register. The Configuration register sets the
persistent operating conditions of the device: the Page
address of the device, selection of mask register for
directly addressed memory writes, and selection between
hardware and software control.
When Hardware control is selected, control is through the
AC bus and DSC line. When Software control is selected,
control is through the Instruction register, which is loaded
from the DQ bus. Under software control the /AV line is
used to distinguish between data and an instruction on the
DQ bus. Therefore, in Software Control mode, random
access to the Memory array can take place only using
indirect addressing through the Address register.
The two Chip Select lines /CS1, /CS2 enable the device
and simplify access to a multi-chip system, if either Chip
Select line is LOW the device is selected. The MU9C RCP
also can be selected through the Device Select register
when its value is set to that of the Page address of the
device, and the enable bit in the Device Select register is
set LOW. The /OE input enables the output signal and is
used to synchronize devices in a multi-chip system, and to
prevent race conditions among devices during priority
resolution.
The output signals comprise the Active address (AA bus),
and the Page address (PA bus). The PA:AA bus provides
the current Active address, which is either the Match
address, Next Free address, or the Random Access
address, concatenated with the Device Page address. The
source of Active address is dependent on the previous
8
control state, allowing access to associated data in the
external RAM at the same location as an access in the
MU9C RCP for all types of cycles.
The Output enable, /OE, controls the PA:AA bus: when it
is LOW after a Compare cycle, the highest-priority
responding device outputs its Page and Match addresses
on PA:AA bus. Only the highest-priority responding
device is enabled, all other lower-priority devices will
have their PA:AA bus in the high-impedance state,
regardless of the state of their respective /OE lines: when
/OE is HIGH, the PA:AA remain in the high-impedance
state.
When a mismatch occurs in the system, the lowest-priority
device, as defined in the Configuration register, will drive
the PA:AA bus with all 1s. When any Read or Write cycle
occurs, the address of the accessed location is output on
the PA:AA bus. The address output on the PA:AA bus is
persistent, and is held latched until /E goes HIGH during
the next cycle that changes the Active address. The PA:AA
bus is free to change only while /E is HIGH. Once /E goes
LOW, the state of the PA:AA bus is latched.
After a Compare cycle, the /MF and /MM flags are free to
change after /E has gone HIGH. Once the Match Flag
daisy chain has resolved device prioritization, the /OE
lines can be asserted to enable the PA:AA bus from the
highest-priority matching device.
In a multi-chip system, when a device remains deselected
during a Compare cycle through /CS1 and /CS2 being
HIGH and there being no match between the Device
Select register and the Page Address register, that device
will clear any previous positive match results. In other
words, if it had previously been indicating a match from
an earlier Comparison cycle, it will now be set to indicate
a mismatch, even though it was not selected during the
most recent Compare cycle.
For pure software control of the MU9C RCP, instructions
can be loaded into the Instruction register, and results read
from the Status register. The Status register holds the
results of comparison: PA:AA bus, /MF, /FF, and /MM
plus two PA:AA Validation bits that indicate the type of
cycle that generated the PA:AA bus value.
Vertical cascading is supported through a daisy chain
architecture. There are two daisy chains, one each for the
Match flag and the Full flag; the Multiple Match flag is
connected between devices through an open-drain line.
The Match flag (/MF) from a higher-priority device is
connected to the Match input (/MI) of the next
lower-priority device to provide prioritization throughout
a multiple device system. The /MF output from the
Rev. 8.04
MUSIC [ MUSIC SEMICONDUCTORS ]
