Operational Characteristics
lowest-priority device provides a system Match flag. If the
delay through the daisy chain is unacceptable, the /OE
input can be used by external priority-resolution circuitry
to enable the highest-priority responder in the system.
The match conditions on the Match and Multiple Match
flag lines are persistent indicating the results of the most
recent Compare cycle. The Match flags are free to change
after the rising edge of /E during a Compare cycle, at
which time the daisy chain starts to resolve device
prioritization. Once the daisy chain has settled, the /OE
lines can be pulled LOW to access the Highest-Priority
Match address on the PA:AA bus.
The Multiple Match open-drain output (/MM) provides
multiple match indication when there are two or more
matches in a single device, or a device has its /MI input
LOW and has a match; the /MM flags of all devices in the
MU9C RCP Family
system are wire-ORed. Multiple responders can be
accessed sequentially by resetting the Highest-Priority
Match latch with the control state Advance to Next
Matching Location.
The Full flag (/FF) is cascaded from one device to the Full
Flag input (/FI) of the next lower-priority device in the
system. The /FF output from the lowest-priority device
provides a system Full flag. The Full flag is free to change
after the rising edge of /E during a Write cycle. The daisy
chains are persistent and are not conditioned by the /OE
input.
The MU9C RCP supports JTAG boundary-scan testing
through the pins TCK, TMS, TDI, TDO, and /TRST,
according to the IEEE 1149 Standard: Test Access Port
and Boundary-scan Architecture.
OPERATIONAL CHARACTERISTICS
Processor Interface
The processor interface is supported through a 32-bit data
bus DQ31-0 and control signals comprised of Chip Enable
(/E), two Chip Selects (/CS1, /CS2), Write Enable (/W),
Output Enable (/OE), Validity Bit Control (/VB), Address
Valid (/AV), Data Segment Control (DSC), and
Address/Control inputs (AC bus). When the /AV line is
LOW, the DSC and AC bus carries an address for random
access into the Memory array; when it is HIGH, the AC
bus conveys control information.
Most of the functionality of the MU9C RCP is accessed
through the control states on DSC and AC bus when /AV
is HIGH. The processor maps the control structure into
memory space and controls the MU9C RCP through
memory Read and Write cycles. Using this memory
mapping scheme, the /AV line should be driven from logic
that generates a HIGH level within the mapped range of
the control states, and a LOW level outside it. Other
control inputs /E, /W, /CS1, and /CS2 are analogous to
SRAM control inputs.
The /VB line acts like an extra data bit during memory
Read and Write cycles and is used to read and write the
validity of any memory location.
The MU9C RCP is enabled either through hardware
through /CS1 or /CS2 being LOW, or it is enabled by the
value written to the Device Select register matching with
the Page Address field of the Configuration register. One
extra bit in the Device Select register enables the
comparison between the Page Address value and the
Device Select register. These Chip Select mechanisms
operate in parallel. If any one is active, the device is
enabled.
Rev. 8.04
The MU9C RCP can be controlled directly through
software. The Software Control mode is selected through
settings in the Configuration register.
When the Software Control mode is selected, control
states are written to the Instruction register from DQ11-0
during a Write cycle with the /AV line held HIGH. DQ12
acts as the DSC input. If the control state does not involve
any data transaction on the DQ31-0 lines, the instruction is
executed during the same cycle; the state of DQ13
modifies the instruction, its state is equivalent to the /W
input.
Note:
It is up to the system designer to ensure that the correct
cycle type follows the loading of an instruction in Software
Control mode. If the instruction expects a Read cycle, and a
Write cycle is executed, or vice versa, the function of the MU9C
RCP is undefined. Such an error may lead to data loss, but will
not damage the device physically.
A Read cycle with the /AV line HIGH will access the
Status register, allowing results to be read back without
loading a new instruction. After a Comparison cycle,
Write at Next Free Address cycle or Read/Write at
Highest-Priority match in a vertically cascaded system,
only the highest-priority device will enable its DQ31-0
lines and output the contents of its Status register. After a
Comparison cycle, in the event of a mismatch in the
MU9C RCP, the DQ31-0 lines of the lowest-priority
device will be enabled. After a random access Read or
Write cycle, the Status register of any selected device will
be enabled. Under these circumstances, it is up to the user
to ensure that only a single device is enabled through
/CS1, /CS2, or the Device Select register.
9
MUSIC [ MUSIC SEMICONDUCTORS ]
