NanoAmp Solutions, Inc.
Functional Block Diagram
N02L083WC2A
Address
Inputs
A
0
- A
3
Word
Address
Decode
Logic
Word Mux
Input/
Output
Mux
and
Buffers
Address
Inputs
A
4
- A
17
Page
Address
Decode
Logic
16K Page
x 16 word
x 8 bit
RAM Array
I/O
0
- I/O
7
CE1
CE2
WE
OE
Control
Logic
Functional Description
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
L
H
H
OE
X
X
X
2
L
H
I/O
0
- I/O
7
High Z
High Z
Data In
Data Out
High Z
MODE
Standby
1
Standby
Write
Read
Active
POWER
Standby
Standby
Active
Active
Active
1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated
from any external influence and disabled from exerting any influence externally.
2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance
1
Item
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
Min
Max
8
8
Unit
pF
pF
1. These parameters are verified in device characterization and are not 100% tested
(DOC# 14-02-015 REV E ECN# 01-0998)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
