NanoAmp Solutions, Inc.
Block Diagram (16Mb x 16)
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
Control Logic
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Bank1
Row-Address MUX
Bank0
Row-Address Latch
& Decoder
Bank2
Bank3
CK, CK
DLL
Mode
Registers
13
8192
Read Latch
Refresh Counter 13
16
16
MUX
16
DQS
Generator
1
Sense Amplifiers
Bank Control Logic
8192
32
Drivers
15
13
Bank0
Memory
Array
(8192 x 256 x 32)
Data
Address Register
COL0
I/O Gating
DM Mask Logic
256
(x32)
2
32
2
Column
Decoder
8
9
Column-Address
Counter/Latch
1
COL0
16
32
16
clk clk
out in Data
CK,
CK
COL0
16
16
16
1
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Receivers
A0-A12,
BA0, BA1
2
32
Write
FIFO
&
Drivers
15
Input
Register
1
Mask 1
1
1
1
DQS
DQ0-DQ15,
LDM, UDM
LDQS,UDQS
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
7
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
