µPD6376
2. INPUT SIGNAL FORMAT
•
Input data must be input as 2’s complement, MSB first.
2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See
the table below.
2’s Complement
L.OUT, R.OUT Pin Voltage TYP. (V)
Decimal Number
Note
(MSB)
0111
0111
(LSB)
1111
(Reference Values)
1111
1111
1111
+32767
+32766
2.6
1.6
0.6
1111
1110
0000
0000
1111
0000
0000
1111
0000
0000
1111
0001
0000
1111
+1
0
–1
1000
1000
0000
0000
0000
0000
0001
0000
–32767
–32768
Note When A.VDD = 5.0 V
Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature.
•
•
Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of
CLK.
CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same
as 1 clock cycle.
5
NEC [ NEC ]
