µPD6376
2.1 Supplying Clock to CLK even outside Sample Data Interval
2.1.1 Serial data input (Pin 1 is Low or Open)
Synchronize the reverse timing of LRCK with the falling edge of CLK upon completion of LSB input (Point A inFigure
2-1).
Figure 2-1 Timing Chart for Serial Data Input
A
A
Interval of 1 sample data
CLK
SI
LSB
16
MSB
LSB
MSB
1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
2
3
4
LRCK
2.1.2. Inputting parallel data (Pin 1 is High)
Synchronize the timing of the falling edge of WDCK with the falling edge of CLK upon completion of LSB input of
data (LSI, RSI) (Point A in Figure 2-2.).
Figure 2-2 Parallel Data Input Timing Chart
A
A
CLK
LSI
LSB
MSB
1
LSB
MSB
1
16
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16
2
2
LSB
16
MSB
1
LSB
MSB
1
10 11 12 13 14 15 16
RSI
WDCK
6
NEC [ NEC ]
