SEMICONDUCTOR
4PT Series
RoHS
RoHS
Fig.3 Average and DC on-state current versus
ambient temperature (DPAK)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
IPAK
DC
α=180°
I
T
(AV)(A)
Device mounted on FR4 with
recommended pad layout
DC
α=180°
DPAK (S = 0.5
cm
²)
1E+0
Fig.4 Relative variation of thermal impedance
junction to ambient versus pulse duration
(DPAK)
K=[Zth(j-c)/Rth(j-c)]
Z th(j-c)
1E-1
Z th(j-a)
1E-2
Device mounted on FR4 with
recommended pad layout
T amb (°C)
50
75
100
125
1E-3
1E-3
t p (s)
1E-2
1E-1
1E+0
1E+1
1E+2
5E+2
Fig.5 Relative variation of gate trigger current
and holding current versus junction
temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
Fig.6 Relative variation of holding current
versus gate-cathode resistance
(typical values)
I
H
[R
GK
] / I
H
[R
GK
=1KΩ
5
4
Tj=25
°
C
I
GT
,I
H
,I
L
[Tj] / I
GT
,I
H
,I
L
[Tj=25 C]
I
GT
l
hand
IL
R
GK
=1K
3
2
T j (°C)
-20
0
20
40
60
80
100
120
140
1
R
GK
(K )
0
1E-2
1E-1
1E+0
1E+1
Fig.7 Relative variation of dV/dt immunity
versus gate-cathode resistance
(typical values)
10.00
Fig.8 Relative variation of dV/dt immunity
versus gate-cathode capacitance
(typical values)
10
8
dV/dt[R
GK
] / dV/dt[R
GK
=220Ω]
Tj=125 C
V
D
=0.67 X V
DRM
dV/dt[C
GK
] / dV/dt[R
GK
=220Ω]
V
D
=0.67 X V
DRM
T
j
=125
°
C
R GK =220
1.00
6
4
0.10
2
0.01
R
GK
(KΩ)
0
0
2
4
6
8
C
GK
(nF)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
10
12
14
16
18
20
22
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