SEMICONDUCTOR
8PT Series
RoHS
RoHS
Fig.7 Relative variation of gate trigger and
holding current versus junction
temperature
Fig.8 Relative variation of holding current
versus gate-cathode resistance
(typical values)
I
H
[R
GK
] / I
H
[R
GK
=1KΩ]
T
j
=25 C
2.4
2.2
I
GT
2.0
1.8
1.6
1.4
1.2
l
H
& I
L
1.0
0.8
0.6
0.4
0.2
0.0
0
-40 -20
I
GT
,I
H
,I
L
[Tj] / I
GT
,I
H
,I
L
[Tj=25
°
C]
5mA & 15mA
T j (°C)
20
40
60
80
100
120 140
6.0
5.5
I
GT =200µA
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1E-2
R
GK
(KΩ)
1E-1
1E+0
1E+1
Fig.9 Relative variation of dV/dt immunity
versus gate-cathode resistance
(typical values) for I
G
=200µA
10.00
Fig.10 Relative variation of dV/dt immunity
versus gate-cathode capacitance
(typical values) for I
GT
=200µA
15.0
12.5
10.0
7.5
5.0
2.5
dV/dt[R
GK
] / dV/dt[R
GK
=220Ω]
T
j
=125
°
C
V
D
=0.67 X V
DRM
dV/dt[C
GK
] / dV/dt[R
GK
=220Ω]
V
D
=0.67 X V
DRM
T
j
=125 C
R
GK
=220Ω
1.00
0.10
0.01
0
200
R
GK
(KΩ)
0.0
0
20
40
60
80
C
GK
(nF)
100 120 140 160 180 200 220
400 600 800 1000 1200 1400 1600 1800 2000
Fig.11 Surge peak on-state current versus
number of cycles
I
STM
(A)
100
90
80
70
60
50
40
30
20
10
0
1
Repetitive
Tc=110
°
C
Non repetitive
T
j
initial=25
°
C
Fig.12 Non-repetitive surge peak on-state current
and corresponding values of l²t
I
TSM
(A),I²t(A²s)
Tj inital=25 C
1000
t
p
=10ms
One cycle
I
TSM
dI/dt Iimitation
100
Sinusoidal pulse with width tp< 10ms
I²t
Number of cycles
10
100
1000
10
0.01
0.10
t p (ms)
1.00
10.00
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