SM8578BV
Control Register 2 (Register F)
This register controls the clock timing frequency divider.
Address
F
I
Bit7
*
Bit6
TEST
Bit5
*
Bit4
RESET
Bit3
HOLD
Bit2
*
Bit1
*
Bit0
*
I
I
I
TEST bit: NPC Test Bit
This bit should be set to “0” when power is applied and when writing to register F.
RESET bit
When this bit is set to “1”, the 2kHz to 1Hz frequency divider counters are reset and clock timing stops.
After “1” data is written, test mode is cancelled by writing “0” data or by setting the CE input LOW.
It is not affected by the state of any other bits.
HOLD bit
When this bit is set to “1”, the seconds digit increment operation is disabled.
However, if an increment operation occurs when this bit is “1” and the bit is subsequently set to “0” within 1
second, the automatic correction function forces a 1-second correction.
Therefore, it is recommended that the HOLD bit should be used for less than 1 second.
Functional operation table
The function of the RESET and HOLD bits is shown in the following table.
Bit
RESET
0
0
1
1
HOLD
0
1
0
1
Clock timing
Operating
*1
Function
Timer interrupt output
Operating
*2
*3
*3
Alarm interrupt output
Operating
Stopped
Stopped
Stopped
Arbitrary frequency
output
Operating
Operating
*4
*4
Stopped
Stopped
*1. The automatic correction function operates if the HOLD bit is set for less than 1 second.
*2. Normal operation for source clocks other than 1/60Hz (1 minute).
*3. Normal operation for 4096Hz source clock only.
*4. Normal operation for 32768Hz source clock only.
NIPPON PRECISION CIRCUITS INC.—10
NPC [ NIPPON PRECISION CIRCUITS INC ]
