ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) (Note 3)
Voltage
Logic Control Inputs
At Other Input and Outputs
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
6.5V
−0.3V to +18V
−0.3V to (V
CC
+0.3V)
260˚C
300˚C
215˚C
Infrared (15 seconds)
Storage Temperature Range
Package Dissipation at T
A
=25˚C
ESD Susceptibility (Note 10)
220˚C
−65˚C to +150˚C
875 mW
800V
Operating Ratings
(Notes 1, 2)
Temperature Range
ADC0804LCJ
ADC0801/02/03/05LCN
ADC0804LCN
ADC0802/04LCWM
Range of V
CC
T
MIN
≤T
A
≤T
MAX
−40˚C≤T
A
≤+85˚C
−40˚C≤T
A
≤+85˚C
0˚C≤T
A
≤+70˚C
0˚C≤T
A
≤+70˚C
4.5 V
DC
to 6.3 V
DC
Electrical Characteristics
The following specifications apply for V
CC
=5 V
DC
, T
MIN
≤T
A
≤T
MAX
and f
CLK
=640 kHz unless otherwise specified.
Parameter
ADC0801: Total Adjusted Error (Note 8)
ADC0802: Total Unadjusted Error (Note 8)
ADC0803: Total Adjusted Error (Note 8)
ADC0804: Total Unadjusted Error (Note 8)
ADC0805: Total Unadjusted Error (Note 8)
V
REF
/2 Input Resistance (Pin 9)
Analog Input Voltage Range
DC Common-Mode Error
Power Supply Sensitivity
Conditions
With Full-Scale Adj.
(See Section 2.5.2)
V
REF
/2=2.500 V
DC
With Full-Scale Adj.
(See Section 2.5.2)
V
REF
/2=2.500 V
DC
V
REF
/2-No Connection
ADC0801/02/03/05
ADC0804 (Note 9)
(Note 4) V(+) or V(−)
Over Analog Input Voltage
Range
V
CC
=5 V
DC
±
10% Over
Allowed V
IN
(+) and V
IN
(−)
Voltage Range (Note 4)
2.5
0.75
Gnd–0.05
8.0
1.1
V
CC
+0.05
Min
Typ
Max
Units
LSB
LSB
LSB
LSB
LSB
kΩ
kΩ
V
DC
LSB
LSB
±
1
⁄
4
±
1
⁄
2
±
1
⁄
2
±
1
±
1
±
1/16
±
1/16
±
1
⁄
8
±
1
⁄
8
AC Electrical Characteristics
The following specifications apply for V
CC
=5 V
DC
and T
MIN
≤T
A
≤T
MAX
unless otherwise specified.
Symbol
T
C
T
C
f
CLK
CR
t
W(WR)L
t
ACC
t
1H
, t
0H
Parameter
Conversion Time
Conversion Time
Clock Frequency
Clock Duty Cycle
Conversion Rate in Free-Running
Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State)
t
WI
, t
RI
C
IN
Delay from Falling Edge
of WR or RD to Reset of INTR
Input Capacitance of Logic
Control Inputs
3
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Conditions
f
CLK
=640 kHz (Note 6)
(Notes 5, 6)
V
CC
=5V, (Note 5)
INTR tied to WR with
CS =0 V
DC
, f
CLK
=640 kHz
CS =0 V
DC
(Note 7)
C
L
=100 pF
C
L
=10 pF, R
L
=10k
(See TRI-STATE Test
Circuits)
Min
103
66
100
40
8770
100
Typ
Max
114
73
Units
µs
1/f
CLK
kHz
%
conv/s
ns
640
1460
60
9708
135
125
200
200
ns
ns
300
5
450
7.5
ns
pF
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