COP8AME9
12.0 Timers
(Continued)
12.4 TIMER T2 OPERATION IN IDLE MODE
Timer T2 has a special mode that allows it to be operated in
IDLE mode. To use this mode, T2 must be configured as a
high speed timer, by setting T2HS = 1, and, also, configured
to run in the IDLE mode by setting the T2IDLE bit to 1 in the
HSTCR register.
shows the modes of operation
allowed for T2 during the IDLE mode. All the T2 modes are
allowed except the following:
•
Using the instruction cycle clock (t
c
)
•
PWM: TxA Toggle
T2 should not be left in this special mode when entering
HALT. The T2IDLE bit must be reset to 0 before entering the
HALT mode to ensure that T2 remains in the same state
when exiting HALT as it was prior to entering HALT.
TABLE 16. Timer T2 Mode Control Bits in IDLE Mode
Mode
TxC3
1
1
1
0
2
0
0
TxC2
0
0
0
0
1
TxC1
1
0
0
1
0
Description
Not Allowed
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
1
1
0
Captures:
TxA Pos. Edge
3
TxB Neg. Edge
0
1
1
Captures:
TxA Neg. Edge
TxB Pos. Edge
1
1
1
Captures:
TxA Neg. Edge
TxB Neg. Edge
12.4.1 Timer T2 Clocking Scheme
shows the relationship between the T2 clock, the
Processor clock, and the T0 clock. Note that the T2 clock is
always equal to the processor clock frequency when en-
abled.
TABLE 17. Timer T2 Clocking Scheme
Device Clock Mode
High Speed
Dual Clock
Low Speed
Idle Mode
0
1
0
1
0
1
T0 Clock
HS Clock
HS Clock
LS Clock
LS Clock
LS Clock
LS Clock
Procesor
Clock
HS Clock
Off
HS Clock
Off
LS Clock
Off
T2 Clock if
T2IDLE = 1
HS Clock
HS Clock
HS Clock
HS Clock
LS Clock
LS Clock
T2 Clock if
T2IDLE = 0
HS Clock
Off
HS Clock
Off
LS Clock
Off
Autoreload RA
Timer Underflow
Timer Underflow
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxB
Edge
MCLK
Pos. TxB
Edge
MCLK
Pos.TxB
Edge
MCLK
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Pos. TxB Edge
MCLK
TxA Pos.
Edge
TxA Neg.
Edge
MCLK
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
35
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