DAC0830/DAC0832
DAC0830 Series Application Hints
(Continued)
Pulling WR
2
low will then update the analog output. A logic
“1” on either of these lines will prevent the changing of the
analog output.
00560807
ILE=LOGIC “1”; WR2 and XFER GROUNDED
FIGURE 4.
1.2 Single-Buffered Operation
In a microprocessor controlled system where maximum data
throughput to the DAC is of primary concern, or when only
one DAC of several needs to be updated at a time, a
single-buffered configuration can be used. One of the two
internal registers allows the data to flow through and the
other register will serve as the data latch.
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in
Single-buffering in a “stand-alone” system is achieved by
strobing WR
1
low to update the DAC with CS, WR
2
and
XFER grounded and ILE tied high.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor inter-
face compatibility, the MICRO-DAC’s can easily be config-
ured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
cations where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
Simply grounding CS, WR
1
, WR
2
, and XFER and tying ILE
high allows both internal registers to follow the applied digital
inputs (flow-through) and directly affect the DAC analog
output.
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be con-
sidered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is
adequate if V
CC
=15V
DC
. A second consideration is that the
guaranteed minimum data hold time of 50ns should be met
or erroneous data can be latched. This hold time is defined
as the length of time data must be held valid on the digital
inputs
after
a qualified (via CS) WR strobe makes a low to
high transition to latch the applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow
memory or peripheral and utilize a technique to extend the
write strobe. A simple extension of the write time, by adding
a wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse-
width. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered
one-shot can be included between the system write strobe
and the WR pin of the DAC. This is illustrated in
for
an exemplary system which provides a 250ns WR strobe
time with a data hold time of less than 10ns.
The proper data set-up time prior to the latching edge (LO to
HI transition) of the WR strobe, is insured if the WR pulse-
width is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may flow
out of the current output terminals. This spike is caused by
the rapid switching of internal logic gates that are responding
to the input changes.
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register
as the latch. Second, reducing the V
CC
supply for the DAC
from +15V to +5V offers a factor of 5 improvement in the
magnitude of the feedthrough, but at the expense of internal
logic switching speed. Finally, increasing C
C
to a
value consistent with the actual circuit bandwidth require-
ments can provide a substantial damping effect on any
output spikes.
11
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
