M25P05-A
Table 4.
Instruction
WREN
WRDI
RDID
(1)
RDSR
WRSR
READ
FAST_READ
PP
SE
BE
DP
Instructions
Instruction set
Description
Write enable
Write disable
Read identification
Read status register
Write status register
Read data bytes
Read data bytes at higher
speed
Page program
Sector erase
Bulk erase
Deep power-down
Release from deep power-
down, and read electronic
signature
Release from deep power-
down
One-byte instruction Address Dummy
code
bytes
bytes
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
06h
04h
9Fh
05h
01h
03h
0Bh
02h
D8h
C7h
B9h
0
0
0
0
0
3
3
3
3
0
0
0
1010 1011
ABh
0
0
0
0
0
0
0
0
0
1
0
0
0
0
3
Data
bytes
0
0
1 to 3
1 to
∞
1
1 to
∞
1 to
∞
1 to 256
0
0
0
1 to
∞
RES
1. The read identification (RDID) instruction is available only in products with process technology code X and
Y (see application note AN1995).
6.1
Write enable (WREN)
The write enable (WREN) instruction (Figure
7)
sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every page program (PP), sector erase
(SE), bulk erase (BE) and write status register (WRSR) instruction.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
Write enable (WREN) instruction sequence
S
0
C
Instruction
D
High Impedance
Q
AI02281E
1
2
3
4
5
6
7
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NUMONYX [ NUMONYX B.V ]
