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M25P05-AVMN6G 参数 Datasheet PDF下载

M25P05-AVMN6G图片预览
型号: M25P05-AVMN6G
PDF下载: 下载PDF文件 查看货源
内容描述: 512千位,串行闪存, 50MHz的SPI总线接口 [512 Kbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 52 页 / 1092 K
品牌: NUMONYX [ NUMONYX B.V ]
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Instructions
M25P05-A
6.2
Write disable (WRDI)
The write disable (WRDI) instruction (Figure
resets the write enable latch (WEL) bit.
The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The write enable latch (WEL) bit is reset under the following conditions:
Power-up
Write disable (WRDI) instruction completion
Write status register (WRSR) instruction completion
Page program (PP) instruction completion
Sector erase (SE) instruction completion
Bulk erase (BE) instruction completion.
Write disable (WRDI) instruction sequence
S
0
C
Instruction
D
High Impedance
Q
AI03750D
Figure 8.
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