欢迎访问ic37.com |
会员登录 免费注册
发布采购

M25P16-VMN3TG 参数 Datasheet PDF下载

M25P16-VMN3TG图片预览
型号: M25P16-VMN3TG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位串行闪存, 75 MHz的SPI总线接口 [16 Mbit, serial Flash memory, 75 MHz SPI bus interface]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 55 页 / 1057 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号M25P16-VMN3TG的Datasheet PDF文件第8页浏览型号M25P16-VMN3TG的Datasheet PDF文件第9页浏览型号M25P16-VMN3TG的Datasheet PDF文件第10页浏览型号M25P16-VMN3TG的Datasheet PDF文件第11页浏览型号M25P16-VMN3TG的Datasheet PDF文件第13页浏览型号M25P16-VMN3TG的Datasheet PDF文件第14页浏览型号M25P16-VMN3TG的Datasheet PDF文件第15页浏览型号M25P16-VMN3TG的Datasheet PDF文件第16页  
Operating features
M25P16
4
4.1
Operating features
Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration t
PP
).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration t
SE
or t
BE
).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (t
W
, t
PP
, t
SE
, or t
BE
). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I
CC2
. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see
This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
12/55