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M25P16-VMN3TG 参数 Datasheet PDF下载

M25P16-VMN3TG图片预览
型号: M25P16-VMN3TG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位串行闪存, 75 MHz的SPI总线接口 [16 Mbit, serial Flash memory, 75 MHz SPI bus interface]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 55 页 / 1057 K
品牌: NUMONYX [ NUMONYX B.V ]
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Operating features
Table 2.
Protected area sizes
Memory content
M25P16
Status Register
content
BP2 BP1 BP0
bit bit bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
Upper 32nd (Sector 31)
Protected area
Unprotected area
All sectors
(1)
(32 sectors: 0 to 31)
Lower 31/32nds (31 sectors: 0 to 30)
Upper sixteenth (2 sectors: 30 and 31) Lower 15/16ths (30 sectors: 0 to 29)
Upper eighth (4 sectors: 28 to 31)
Upper quarter (8 sectors: 24 to 31)
Upper half (16 sectors: 16 to 31)
All sectors (32 sectors: 0 to 31)
All sectors (32 sectors: 0 to 31)
Lower seven-eighths (28 sectors: 0 to 27)
Lower three-quarters (24 sectors: 0 to 23)
Lower half (16 sectors: 0 to 15)
none
none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
4.7
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low (this is shown in
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
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