1 Summary description
M36P0R9060E0
1
Summary description
The M36P0R9060E0 combines two memory devices in a Multi-Chip Package:
●
●
512-Mbit Multiple Bank Flash memory (the M58PR512J)
64-Mbit PSRAM
(the M69KB096AM)
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58PRxxxJ and
M69KB096AM datasheets, where all specifications required to operate the Flash memory
and PSRAM components are fully detailed. These datasheets are available from the
Numonyx website:
www.numonyx.com.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bits
erased (set to ‘1’).
Figure 1.
Logic diagram
V
DDF
V
DDQ
25
A0-A24
E
F
G
F
W
F
RP
F
WP
F
L
K
DPD
F
E
P
G
P
W
P
CR
P
UB
P
LB
P
V
CCP
V
PPF
16
DQ0-DQ15
WAIT
M36P0R9060E0
V
SS
AI10994
6/23
NUMONYX [ NUMONYX B.V ]
