M36P0R9060E0
2 Signal descriptions
2
Signal descriptions
See
and
for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A24)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components.
Addresses A22 and A24 are inputs for the Flash memory component only. The Address
Inputs select the cells in the Flash memory array to access during Bus Read operations.
During Bus Write operations they control the commands sent to the Command Interface of
the Flash memory’s Program/Erase Controller.
In the PSRAM the Address Inputs select the cells in the memory array to access during Bus
read and write operations.
2.2
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the
data to or from the upper part of the selected address when Upper Byte Enable (UB
P
) is
driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the
lower part of the selected address when Lower Byte Enable (LB
P
) is driven Low. When both
UB
P
and LB
P
are disabled, the Data Inputs/ Outputs are high impedance.
2.3
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the
Flash memory.
2.4
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the Flash
memory.
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NUMONYX [ NUMONYX B.V ]
