Description
M45PE10
1
Description
The M45PE10 is a 1-Mbit (128 Kbit x 8 bit) serial paged flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the page write or
page program instruction. The page write instruction consists of an integrated page erase
cycle followed by a page program cycle.
The memory is organized as 2 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The memory can be erased a page at a time, using the page erase instruction, or a sector at
a time, using the sector erase instruction.
Important note
This datasheet details the functionality of the M45PE10 devices, based on the previous T7X
process or based on the current T9HX process (available since August 2007). Delivery of
parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
Figure 1.
Logic diagram
VCC
D
C
S
W
Reset
M45PE10
Q
VSS
AI07403
Figure 2.
SO and VDFPN connections
M45PE10
D
C
Reset
S
1
2
3
4
8
7
6
5
AI07404
Q
VSS
VCC
W
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
V
SS
, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See
section for package dimensions, and how to identify pin-1.
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NUMONYX [ NUMONYX B.V ]
