M58LT256JST8ZA6 参数 Datasheet PDF下载

Hi-Z

VALID

VALID

VALID

VALID

DQ0-DQ15

M58LT256JST, M58LT256JSB

A0-A23

VALID ADDRESS

tAVLH

tLLLH

L

tEHQX

tKHQV

Note 1

Note 3

tEHEL

tEHQZ

tLLKH

tAVKH

K

(4)

tELKH

tKHAX

E

tGLQX

tGLQV

tGHQZ

tGLQV

tGHQX

tGHQZ

Figure 13. Synchronous burst read suspend AC waveforms

G

tGLTV

tGHTZ

tGLTV

tEHTZ

Hi-Z

WAIT

(2)

DC and AC parameters

Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

3. The CLOCK signal can be held high or low

4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.

Here, the active edge is the rising one.

AI13724

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