DC and AC parameters
Table 24.
Symbol
t
AVAV
t
AVLH
t
AVWH(3)
t
DVWH
t
ELLH
t
ELWL
Write Enable Controlled timings
t
ELQV
t
ELKV
t
GHWL
t
LHAX
t
LLLH
t
WHAV(2)
t
WHAX(2)
t
WHDX
t
WHEH
t
WHEL(3)
t
WHGL
t
WHLL(3)
t
WHWL
t
WLWH
Protection timings
t
QVVPL
t
VPHWH
t
WHVPL
t
VPS
t
AH
t
DH
t
CH
t
CS
t
DS
M58LT256JST, M58LT256JSB
Write AC characteristics, Write Enable controlled
(1)
M58LT256JST/B
Alt
t
WC
Parameter
85
Address Valid to Next Address Valid
Address Valid to Latch Enable High
Address Valid to Write Enable High
Data Valid to Write Enable High
Chip Enable Low to Latch Enable High
Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
Chip Enable Low to Clock Valid
Output Enable High to Write Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
Write Enable High to Address Valid
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Latch Enable Low
t
WPH
Write Enable High to Write Enable Low
t
WP
Write Enable Low to Write Enable High
Output (Status Register) Valid to V
PP
Low
V
PP
High to Write Enable High
Write Enable High to V
PP
Low
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
85
10
50
50
10
0
85
9
17
9
10
0
0
0
0
25
0
25
25
50
0
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept Low.
3. t
WHEL
and t
WHLL
have this value when reading in the targeted bank or when reading following a Set
Configuration Register command. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing any command and to
delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration
Register have been issued, t
WHEL
and t
WHLL
are 0 ns.
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