M58LT256JST, M58LT256JSB
Signal descriptions
2
Signal descriptions
See
and
for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A23)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the Program/Erase Controller.
2.2
Data input/output (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V
IL
and Reset is at V
IH
the device is in active
mode. When Chip Enable is at V
IH
the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the bus write operation of the memory’s command interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable,
whichever occurs first.
2.6
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V
IL
, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current I
DD2
. Refer to
for
the value of I
DD2.
After Reset all blocks are in the protected state and the Configuration
Register is reset. When Reset is at V
IH
, the device is in normal operation. Upon exiting reset
mode the device enters asynchronous read mode, however, a negative transition of Chip
Enable or Latch Enable is required to ensure valid data outputs.
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NUMONYX [ NUMONYX B.V ]
