NAND02G-B2D
Device operations
6.8
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in
each plane.
This operation consists of the following three steps (refer to Figure 18: Multiplane block
erase):
1. 10 bus cycles are required to set up the Block Erase command and load the addresses
of the blocks to be erased. The Setup command followed by the address of the block to
be erased must be issued for each block. t
busy time is required between the
IEBSY
insertion of first and the second block addresses. As for multiplane page program, the
address of the first and second page must be within the first plane (A18 = 0 for x8
devices, A17 = 0 for x16 devices) and second plane (A18 = 1 for x8 devices, A17 = 1 for
x16 devices), respectively
2. one bus cycle is then required to issue the Multiplane Block Erase Confirm command
and start the P/E/R controller
If the multiplane block erase fails, an error is signaled on bit SR0 of the Status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see Section 6.12).
Figure 18. Multiplane block erase
tBLBH3
(Erase Busy time)
RB
Busy
Block address
inputs
Block address
inputs
I/O
60h
60h
D0h
70h
SR0
A18=1
A12-A17=0
A17-A29=valid
A18=0
A12-A17=0
A17-A29=0
Block Erase
Setup code
Confirm
code
Read Status
register
Block Erase
Setup code
a) Traditional sequence
CL
W
AL
R
I/O 0-7
60h R1A R2A R3A D1h
tIPBSY
60h R1B R2B R3B
D0h
tBLBH2
(Program Busy time)
RB
Busy
Busy
b) ONFI 1.0 sequence.
ai13173c
1. This address scheme refers to x 8 devices. Please remember to use the appropriate scheme for x 16 devices.
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