DC and AC parameters
NAND02G-B2D
Figure 42. Resistor value versus waveform timings for ready/busy signal
V
= 3.3 V, C = 100 pF
V
= 1.8 V, C = 30 pF
L
DD
L
DD
400
300
200
4
3
2
400
300
4
3
2
400
300
2.4
200
1.7
200
1.2
120
1
90
100
0
1
100
30
0.8
3.6
0.85
100
3.6
0.57
0.6
3.6
0.43
1.7
60
1.7
3.6
1.7
0
1.7
1
2
3
4
1
2
3
4
R
(KΩ)
R
(KΩ)
P
P
t
f
t
r
ibusy
ai13640b
1. T = 25 °C.
11.2
Data protection
The Numonyx NAND devices are designed to guarantee data protection during power
transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
LKO
DD
DD
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
low (V ) to guarantee hardware protection during power transitions as shown in the below
IL
figure.
Figure 43. Data protection
Nominal range
V
DD
V
LKO
Locked
Locked
W
Ai11086
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NUMONYX [ NUMONYX B.V ]
