Numonyx™ Embedded Flash Memory (J3 v. D)
8.0
Bus Interface
This section provides an overview of Bus operations.
Basically, there are three operations you can
do with flash memory: Read, Program (Write), and Erase.The
on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of all in-system read,
write, and erase operations through the system bus.
All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
summarizes the necessary
states of each control signal for different modes of operations.
Table 14: Bus Operations
Mode
Async., Status, Query and Identifier
Reads
Output Disable
Standby
Reset/Power-down
Command Writes
Array Writes
(8)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
RP#
CE
x
(1)
OE#
(2)
WE#
(2)
V
PEN
DQ
15:0(
3)
STS
(Default
Mode)
High Z
High Z
High Z
High Z
High Z
V
IL
Notes
V
IH
V
IH
V
IH
V
IL
V
IH
V
IH
Enabled
Enabled
Disable
d
X
Enabled
Enabled
V
IL
V
IH
X
X
V
IH
V
IH
V
IH
V
IH
X
X
V
IL
V
IL
X
X
X
X
X
V
PENH
D
OUT
High Z
High Z
High Z
D
IN
X
4,6
6,7
8,5
See
for valid CE
x
Configurations.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high.
≤
V
PENLK
, memory contents can be read but not altered.
Refer to DC characteristics. When V
PEN
X should be V
IL
or V
IH
for the control pins and V
PENLK
or V
PENH
for V
PEN
. For outputs, X should be V
OL
or V
OH
.
In default mode, STS is V
OL
when the WSM is executing internal block erase, program, or a lock-bit configuration
algorithm. It is V
OH
(pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase
suspend mode (with programming inactive), program suspend mode, or reset power-down mode.
See
for valid DIN (user commands) during a Write
operation
Array writes are either program or erase operations. /
Table 15: Chip Enable Truth Table
CE2
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
Note:
CE1
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
GND
.
CE0
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
For single-chip applications, CE2 and CE1 can be connected to
The next few sections detail each of the basic flash operations and some of the
advanced features available on flash memory.
November 2007
308551-05
Datasheet
31
NUMONYX [ NUMONYX B.V ]
