PEDL60851C-02
1
Semiconductor
ML60851C
End Point 2 Transmit FIFO (EP2TXFIFO)
Read address
Write address
D7
After a hardware reset
After a bus reset
Definition
x
x
D6
x
x
—
C2h
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
EP2 Transmit data (W)
The EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851C
issues an EP2 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be
invalid.
The EP2 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP2.
2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).
End Point 3 Transmit FIFO (EP3TXFIFO)
Read address
Write address
D7
After a hardware reset
After a bus reset
Definition
x
x
D6
x
x
—
C3h
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
EP3 Transmit data (W)
The EP3 transmit data can be written in by writing to the address C3h. Make the local MCU write the transmit data
in EP3TXFIFO when the ML60851C issues an EP3 packet ready interrupt request. It is possible to write the
packet data successively by writing continuously.
The EP3 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP3.
2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).
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