PEDL60851C-02
1
Semiconductor
ML60851C
FUNCTIONS OF REGISTERS
End Point 0 Receive FIFO (EP0RXFIFO)
Read address
Write address
D7
After a hardware reset
After a bus reset
Definition
x
x
D6
x
x
40h
-
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
EP0 Receive data (R)
The receive data from the host computer in the data state during a control Write transfer is stored in EP0RXFIFO.
The EP0 receive data can be read out by the local MPU through reading the address 40h when the ML60851C
issues an EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by
reading continuously.
The EP2RXFIFO is cleared under the following conditions:
1. When the local MPU resets the EP0 receive packet ready bit (A “1” is written in PKTRDY(0)).
2. When a setup packet is received.
3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).
End Point 1 Receive FIFO (EP1RXFIFO)
Read address
Write address
D7
After a hardware reset
After a bus reset
Definition
x
x
D6
x
x
41h
—
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
EP1 Receive data (R)
It is possible to read out the EP1 receive data by reading the address 41h. When EP1 is set for bulk reception
(BULK OUT), The local MCU should read EP1RXFIFO when the ML60851C issues an EP2 packet ready
interrupt request. It is possible to read successively the data in the packet by reading continuously. When the data
transfer direction of EP1 is set as “Transmit”, all accesses to this address will be invalid.
The EP1RXFIFO is cleared under the following conditions:
1. When an OUT token is received for EP1.
2. When the EP1 receive packet ready bit is reset. (A “1” is written in PKTRDY(1).)
3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).
Even when a DMA read with a 16-bit width is made from EP1RXFIFO, the address is A7:A0 = 41h.
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