PEDL60841-01
OKI Semiconductor
ML60841
REGISTER
The registers of the ML60841 are divided mainly into common registers, host controller registers and device
controller registers.
Approximate categorywise map of addresses is as follows.
Category
Common register
Host controller register
Device controller register
Host controller memory
Offset
Remarks
000h−0FFh
100h−2FFh
200h−3FFh
OpenHCI control register included
1000h−1FFFh Internal 4 KB RAM
Mapping of each register is shown on next page onward.
The meanings of “R”, “W”, and “R/W” are the following in the register descriptions given hereafter.
R:
Only read operation is valid. Unless specifically described in the descriptions of the different
registers, there will be no effect on the operations even when a “0” or a “1” is written to the concerned
part.
W:
Only write operation is valid. Unless specifically described in the descriptions of the different
registers, an uncertain data will be returned when the concerned part is read out.
R/W: Both read and write operations are valid.
In the following description of registers, operation cannot be guaranteed when an unspecified address is accessed.
Therefore, control the LSI operation so that such an address will not be accessed. Moreover, since operation
cannot be guaranteed when a “1” is written in an unspecified field of specified registers, write a “0” in an
unspecified field when writing in other fields.
Also, if the device controller registers (registers 300h to 3FFh) are accessed during operations as a host
controller, or if the host controller registers (registers 100h to 2FFh) and host controller memories (1000h to
1FFFh) are accessed during operations as a device controller, the operations of the function being executed
currently (host controller function in the former case and device controller function in the latter case) cannot be
guaranteed and hence controls should be implemented so as not to make such access.
The meaning of “Don’t Care” and “X” is as follows.
When writing: There is no affect on the operation of the ML60841 by writing either “0” or “1”.
When reading: Undefined data is read.
In the ML60841, it is possible to specify combinations of big-endian or little-endian and 16-bit bus width or
32-bit bus width as the data bus specifications. Depending on these combinations, there are some restrictions
on the register (memory) accesses of different blocks. Implement controls to observe the following restrictions.
The operations cannot be guaranteed if these restrictions are not observed.
c
When using a 16-bit bus width, carry out one set of the two accesses to the offset address and offset
address +2 when accessing the host controller registers (including the OpenHCI operation register) and
the host controller memories.
The data is written to the concerned register or memory when the 32-bit data becomes ready within the
ML60841.
d
When using a 16-bit bus width, write data of bits 15:0 to the offset address of a common register in the
case of both the big-endian and the little-endian modes. In other words, when using a 16-bit bus width,
carry out writes using instructions that handle 16-bit data.
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