PEDL60841-01
OKI Semiconductor
ML60841
FEATURES
[Common Section]
•
USB 1.1 compliant
•
Maximum bus clock (BUS_CLK) frequency: 33 MHz
•
Allows host/device selection by an external terminal
•
16-/32-bit bus width selectable
•
Little/Big endian can be selected
•
Common connector use/no use can be selected
•
Occupies 0000h to 1FFFh 8K byte space (registers: 0xxxh, internal RAM: 1000h to 1FFFh)
•
DMA control of high flexibility.
- Supports host mode: 1 channel, device mode: 2 channels
- Supports the following DMA transfer mode
Transfer size: 32 bits (need to specify the same transfer size as that of the microcontroller side DMA
controller)
[Host Controller Section]
•
OpenHCI (Open Host Controller Interface) 1.0a compliant
•
Supports 4 data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer)
•
Built-in 4-Kbyte RAM
•
DMA slave function (1 channel) reduces software load
•
Supports 1 USB port (supports full speed (12 Mbps) and low speed (1.5 Mbps))
•
Supports SOF generation and CRC5/16 bit generation function
[Device Controller Section]
•
Supports full speed (12 Mbps)
•
Supports 4 data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer)
•
End points: 5 or 6
- Control EP
: 1 (EP0)
- Bulk/interrupt EP
: 3 (EP1, EP2, and EP3)
- Isochronous/bulk/interrupt EP : 1 or 2 (EP4 and/or EP5)
•
Built-in FIFO for storing data
•
Double-layer configuration FIFO of EP1, EP2, EP4, and EP5
•
Supports 2-channel DMA slave function (EP1, EP2, EP4, and EP5)
•
Supports Suspend and Wakeup functions.
[Others]
•
USB port can be connected to a USB transceiver LSI
•
48 MHz crystal oscillator
•
3.3 V single power supply
•
Package: 120-pin TQFP (TQFP120-P-1414-0.40-K)
120-pin BGA (P-TFBGA120-0909-0.65)
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