Pin Configuration
ML67Q4050/Q4060 Series
Pin Descriptions (Cont.)
Function Level
1st 2nd 3rd
Symbol
I/O
Description
External Interrupts
EFIQ_N
I
I
Fast Interrupt request (Active-Low)
Interrupt requests
✔
✔
EXINT[5:1]
SPI
MISO[1:0]
MOSI[1:0]
SSN[1:0]
SCK[1:0]
I/O Serial data: Master In – Slave Out
I/O Serial data: Master Out – Slave In
I/O Slave select
✔
✔
✔
✔
I/O Serial clock
I2S
I2S serial data
I/O
SD
✔
✔
✔
I2S bit clock
I/O
SCK
WS
I2S word clock
I/O
[a]
[b]
MCLK
O
Audio Clock Output
I2C
I2C serial data
I2C serial clock
SDA
SCL
I/O
O
✔
✔
A/D Converter
Timer
AIN [3:0]
I
A/D inputs (four channels)
✔
✔
TIMER[5:0]
I/O Timer I/O – Six Channels
Power Supply
VDD_CORE
VDD_IO
Core logic power supply
I/O power supply
—
—
—
—
—
—
GND
Core and I/O ground
PLL power supply
—
—
—
—
—
—
VDD_PLL
GNDPLL
PLL ground
—
—
—
a. The MCLK can be programmed to be available on the PE3 pin.
b. The MCLK can be programmed to be available on the RSTOUT_N pin.
June 2006, Rev 1.2
Oki Semiconductor • 11
OKI [ OKI ELECTRONIC COMPONETS ]
