Pin Configuration
ML67Q4050/Q4060 Series
Figure 3. 64-Pin WCSP for the ML67Q4060/61
Top View of WCSP Package
A
8
BOOTCLK/
PD5
B
NC
C
PF5/
TIMER5/
EXINT5
D
PF2/
TIMER2/
CTS1
E
PE4/
SD
F
PB0/
TX0
G
PB4/
SCL/
TXD
H
PB3/
RX1/
EXINT1
8
7
PC0/
MISO0/
DSR0
GND
PF4/
TIMER4/
EXINT4
PF[1[/
TIMER1/
RTS0
BOOT0/
PE3/
MCLK
PB5/
SDA/
RXD
PE0
VDD_IO
7
GND
PE1
6
PC2/
SCK0/
RI0
PC3/
SSN0/
DCD0
PC4/
MISO1/
DSR1
PF3/
TIMER3/
RTS1
PB2/
TX1/
EFIQ_N
PE2
6
PD1/
AIN1/
EXINT3
PD0/
AIN0/
EXINT2
VDD_IO
5
PC5/
MOSI1/
DTR1
RESET_N
TDI/
PA2
PC1/
MOSI0/
DTR0
PB1/
/RX0
5
TEST1
RSTOUT_N/PA6/
MCLK
4
BS/
PD4
PC6/
SCK1/
RI1
PC7/
SSN1/
DCD1
TMS/
PA1
PF0/
TIMER0/
CTS0
PD2/
AIN2
PD3/
AN3
4
VDD_PLL
PE5/
WS
TDO/
PA3
TCK/
PA0
VDD_IO
TEST2
GND
3
NTRST/
PA4
PE6/
SCK
VDD_CORE
GND
VDD_IO
VDD_CORE
VDD_CORE
GND_PLL
3
2
JTAGE/
PA5
VDD_IO
SYSCLK_N
SYSCLK_P
GND
RTCCLK_P
RTCCLK_N
VDD_CORE
2
1
A
B
C
D
E
F
G
H
1
NOTES:
1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See
Table for details.
June 2006, Rev 1.2
Oki Semiconductor • 7
OKI [ OKI ELECTRONIC COMPONETS ]
