¡ Semiconductor
RSYNC
ML7000-01/02/03/ML7001-01/02/03
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz
±50
ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not
guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz
±50
ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section. However, if the frequency characteristic of
an applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but the
electrical characteristics in this specification are not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
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